Question

FPGA书上的分频器程序，一模一样却仿真不出来，结果一直为0。

module fre(clk,data,fout);
input clk;
input[7:0]data;
output fout;
reg full,cnt,fout;
reg[7:0]cnt8;
always@(posedge clk)
begin
if(cnt8==8'hff)
begin
cnt8=data;
full<=1;
end
else
begin
cnt8=cnt8+1;
full<=1;
end
end
always@(posedge full)
begin
cnt=(!cnt);
if(cnt==1)fout<=1;
else fout<=0;
end
endmodule

Answer 1

这个程序里，full寄存器一直没有被复位。
always@(posedge clk)
begin
if(cnt8==8'hff)
begin
cnt8=data;
full<=1;
end
else
begin
cnt8=cnt8+1;
full<=1;//把这一句改成full<=0试试
end
end