Question

用Verilog HDL编写简单的程序！数电实验！

利用DE0开发板上的50M时钟，用Verilog HDL实现两路分频输出，一路为50M分频占空比50%的1Hz信号输出，另一路5M分频占空比20%的10Hz信号输出。（不做波形仿真）

Answer 1

module clk_div(clk,out1,out2);
input clk;
output out1,out2;
reg out1,out2;
reg [31:0]cnt1,cnt2;

always @(posedge clk)begin//50MHz分频计数
if(cnt1<32'd24999999)
cnt1 <=cnt1 + 32'd1;
else
cnt1 <=32'd0;
end

always @(posedge clk)//分频后的半周期反转
if(cnt1 == 0)
out1<=~out1;

always @(posedge clk)begin//5MHz分频计数
if(cnt2<32'd4999999)
cnt2 <=cnt2 + 32'd1;
else
cnt2 <=32'd0;
end

always @(posedge clk)//20%占空比
if(cnt2 == 32'd999999)
out2<=0;
else if(cnt2 == 32'd4999999)
out2<=1;
endmodule