Question

verilog 10137错误

代码如下
module kai (a ,clk ,b,c,d,h,inv);

input [3:0] a ;
input clk ;
output [3:0] b,c ,d;
output inv,h;
reg [3:0] b,c,d ;
wire h,inv;
always @(posedge clk)
begin
if (inv==0)
b<=a;
else
b<=~a;
end

always @(posedge clk)
begin
c<=b;
end
always @(posedge clk)
begin

d[0] = a[0] ^ c[0];
d[1] = a[1] ^ c[1];
d[2] = a[2] ^ c[2];
d[3] = a[3] ^ c[3];
end
always @(posedge clk)
begin
h=d[0]+d[1]+d[2]+d[3];
end
always @(posedge clk)
begin
if (h>2)
inv=0;
else
inv=1;

end

endmodule
Error (10137): Verilog HDL Procedural Assignment error at kai.v(32): object "h" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at kai.v(37): object "inv" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at kai.v(39): object "inv" on left-hand side of assignment must have a variable data type
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings

Answer 1

verilog不同C，这是C的写法
在
wire h,inv;

下面加入
reg r_h,r_inv;
assign h=r_h;
assign inv=r_inv;

把
h=d[0]+d[1]+d[2]+d[3];

改为
r_h<=d[0]+d[1]+d[2]+d[3];

把
if (h>2)
inv=0;
else
inv=1;
改为
if (h>2)
r_inv<=0;
else
r_inv<=1;