Question

谁能给我个正确的基于EDA的VHDL的八路抢答器的程序？悬赏30分。。。

Answer 1

http://wenku.baidu.com/view/2436c942336c1eb91a375d40.html

追问

下下来的不知道是什么东西，没有这个文档啊。

追答

我下下来了 给我个邮箱

追问

你觉得这个程序是正确的？1095155282@QQ.COM

追答

这是4位的 给你参考一下

Answer 2

一 编码程序：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY change IS
PORT(q1,q2,q3,q4,q5,q6,q7,q8: IN STD_LOGIC;
clr : IN STD_LOGIC;
m: OUT STD_LOGIC_vector(3 downto 0);
en: OUT STD_LOGIC);
END change;
ARCHITECTURE a OF change IS
BEGIN
process(q1,q2,q3,q4,q5,q6,q7,q8,clr)
variable temp:STD_LOGIC_vector(7 downto 0);
begin
temp:=q1&q2&q3&q4&q5&q6&q7&q8;
case temp is
when"01111111"=>m<="0001";
when"10111111"=>m<="0010";
when"11011111"=>m<="0011";
when"11101111"=>m<="0100";
when"11110111"=>m<="0101";
when"11111011"=>m<="0110";
when"11111101"=>m<="0111";
when"11111110"=>m<="1000";
when others=>m<="1111";
end case;
en <= temp(7) AND temp(6) AND temp(5) AND temp(4) AND temp(3) AND temp(2) AND temp(1) AND temp(0) AND clr;
end process;
END a;

二 锁存程序：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY lock IS
PORT(s1: IN STD_LOGIC;
s2: IN STD_LOGIC;
s3: IN STD_LOGIC;
s4: IN STD_LOGIC;
s5: IN STD_LOGIC;
s6: IN STD_LOGIC;
s7: IN STD_LOGIC;
s8: IN STD_LOGIC;
clr: IN STD_LOGIC;
q1,q2,q3,q4,q5,q6,q7,q8: OUT STD_LOGIC);
END lock;
ARCHITECTURE a OF lock IS
BEGIN
process(s1,s2,s3,s4,s5,s6,s7,s8,clr)
begin
if(clr ='0') then
q1<='1';q2<='1';
q3<='1';q4<='1';
q5<='1';q6<='1';
q7<='1';q8<='1';
else
q1<=s1;q2<=s2;
q3<=s3;q4<=s4;
q5<=s5;q6<=s6;
q7<=s7;q8<=s8;
end if;
end process;
END a;

三 抢答成功扬声器发声程序：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY cnt IS
PORT(clk,en: in STD_LOGIC;
sound1:out STD_LOGIC);
END cnt;
ARCHITECTURE a OF cnt IS
BEGIN
process(en,clk)
begin
if(clk'event and clk='1') then
if(en='1') then
sound1<='1';
else
sound1<='0';
end if;end if;
end process;
END a;

四 数码管显示管
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY display IS
PORT(m: IN STD_LOGIC_VECTOR(3 downto 0);
BCD: out STD_LOGIC_VECTOR(7 downto 0));
END display;
ARCHITECTURE a OF display IS
BEGIN
PROCESS(m)
BEGIN
CASE m IS
WHEN "0000" => BCD <="00111111";
WHEN "0001" => BCD <="00000110";
WHEN "0010" => BCD <="01011011";
WHEN "0011" => BCD <="01001111";
WHEN "0100" => BCD <="01100110";
WHEN "0101" => BCD <="01101101";
WHEN "0110" => BCD <="01111101";
WHEN "0111" => BCD <="00000111";
WHEN "1000" => BCD <="01111111";
WHEN "1001" => BCD <="01101111";
WHEN OTHERS => BCD <="00000000";
END CASE;
END PROCESS;
END a;

Answer 3

我来给你说。。。私下M我。