Question

大神们，这是在QUARTUSII中的VHDL程序怎么写TESTBENCH呀 ？用生成模板修改后的回复就可以。。。帮帮忙

LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
Entity nco IS
GENERIC(WIDTH:INTEGER:=28);
PORT(fcw :IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
sin,cos,acc:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clk :IN STD_LOGIC);
END nco;
Architecture rtl OF nco IS
SIGNAL s,acc28: STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
SIGNAL msbs: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sin_cos: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
addl:lpm_add_sub
GENERIC MAP(LPM_WIDTH=>WIDTH,
LPM_REPRESENTATION=>"SIGNED",
LPM_DIRECTION=>"ADD",
LPM_PIPELINE=>0)
PORT MAP(dataa=>fcw,
datab=>acc28,
result=>s);
regl:lpm_ff
GENERIC MAP(LPM_WIDTH=>WIDTH)
PORT MAP(data=>s,
q=>acc28,
clock=>clk);
select1:PROCESS(acc28)
VARIABLE i:INTEGER;
BEGIN
FOR i IN 7 DOWNTO 0 LOOP
msbs(i)<=acc28(27-7+i);
END LOOP;
END PROCESS select1;
acc<=msbs;
rom1:lpm_rom
GENERIC MAP(LPM_WIDTH=>16,
LPM_WIDTHAD=>8,
LPM_FILE=>"sin_cos.mif")
PORT MAP(address=>msbs,
inclock=>clk,
outclock=>clk,
q=>sin_cos);
select2:PROCESS(sin_cos)
VARIABLE i:INTEGER;
BEGIN
FOR i IN 7 DOWNTO 0 LOOP
cos(i)<=sin_cos(11-7+i);
sin(i)<=sin_cos(i);
END LOOP;
END PROCESS select2;
END rtl; 这是源程序

Answer 1

我帮你写吧