哪位高人帮我翻译一下?谢了!(中翻英)

在数字电路理论中,时序逻辑电路是指电路任何时刻的稳态输出不仅取决于当前的输入,还与前一时刻输入形成的状态有关。这跟组合逻辑电路相反,组合逻辑的输出只会跟目前的输入成一种函... 在数字电路理论中,时序逻辑电路是指电路任何时刻的稳态输出不仅取决于当前的输入,还与前一时刻输入形成的状态有关。这跟组合逻辑电路相反,组合逻辑的输出只会跟目前的输入成一种函数关系。换句话说,时序逻辑拥有储存元件(内存)来存储信息,而组合逻辑则没有。
时序逻辑电路可以分为同步时序逻辑电路和异步时序逻辑电路。
同步时序逻辑电路中所有存储元件都在时钟脉冲CP的统一控制下,用触发器作为存储元件。几乎现在所有的时序逻辑都是“同步逻辑”,有一个“时钟”讯号,所有的内部内存(内部状态)只会在时钟的边沿时候改变。在时序逻辑中最基本的储存元件是触发器。
同步逻辑最主要的优点是它很简单。每一个电路里的运算必须要在时钟的两个脉冲之间固定的间隔内完成,称为一个“时钟周期”。指有在这个条件满足下(不考虑其他的某些细节),电路才能保证是可靠的。
同步逻辑也有两个主要的特点:
1. 时钟讯号必须要分布到电路上的每一个触发器。而时钟通常都是高频率的讯号,这会导致功率的消耗,也就是产生热量。即使每个触发器没有做任何的事情,也会消耗少量的能量,因此会导致废热产生。
2. 最大的可能时钟频率是由电路中最慢的逻辑路径决定,也就是关键路径。意思就是说每个逻辑的运算,从最简单的到最复杂的,都要在每一个时脉的周期中完成。一种用来消除这种限制的方法,是将复杂的运算分开成为数个简单的运算,这种技术称为“流水线”。这种技术在微处理器中非常的显著,用来帮助提升现今处理器的时钟频率。
异步时序逻辑电路最基本的储存元件是锁存器,锁存器可以在任何时间改变它的状态,依照其他的锁存器讯号的变动,他们新的状态就会被产生出来。异步电路的复杂度随着逻辑门的增加,而复杂性也快速的增加,因此他们大部分仅仅使用在小的应用。然而,电脑辅助设计工具渐渐的可以简化这些工作,允许更复杂的设计。

我的毕业论文题目是《基于ARM+FPGA的运动控制卡研究》,下面我对论文作一个简单介绍,经典的计算机数控系统(CNC, Computerized Numerical Control)普遍采用模拟电压输出驱动伺服单元,计算机的模拟接口部分线性分立元件多、系统空间庞大、抗干扰能力较差。随着数字电路技术的蓬勃发展,研究全数字化数控系统己经成为必然的趋势。
本课题的研究利用现场可编程门阵列(FPGA,Field Programmable Gate Array)集成度高、体积小、低功耗、高可靠性、可以在线修改等特点,以及利用Verilog HDL语言的程序设计方法、设计灵活、修改方便、可移植性好等特点,来设计数控系统的运动控制芯片。该芯片是运动控制卡的核心部分,能够同时控制4个伺服马达或步进马达的运动,它以脉冲串形式输出,能对伺服马达和步进马达进行位置控制和速度控制。
主要工作包括:(1)对数控系统的研究现状进行分析,确定开发模式。(2)完成整个系统的硬件电路设计,重点是FPGA 模块的设计、验证、修正和定型。 (3)对S型控制曲线进行研究,分析其类型,确定其函数表达式。(4)对主要模块进行调试,给出了实验结果。 (5)对研究内容进行了总结,对运动控制技术的发展作了展望。在设计过程中有几项技术是完成本设计的关键:驱动脉冲宽度和速度精确度和任意整数分频技术等
设计大约需要半年左右的时间来完成,在这半年中,我将学到了很多知识:对NC的轴控制单元会有清楚的认识,能够学会使用EDA电子设计工具,并能够掌握了FPGA和VHDL的知识,具备独立开发中小规模集成电路的能力,对大规模集成电路的开发过程也有深刻的认识。
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缪洲v6
2007-06-27
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In the digital circuit theory, the succession logic circuit is referselectric circuit any time the stable state output not only to bedecided by the current input, but also the condition which forms withprevious time input concerns. This is opposite with the combinatorylogic electric circuit, the combinatory logic output only can with thepresent input one kind of functional relation. In other words, thesuccession logic has stores up the part (memory) the canned data, butthe combinatory logic does not have. The succession logic circuit may divide into the synchronizedsuccession logic circuit and the asynchronous succession logiccircuit. In synchronized succession logic circuit all storage element all inunder clock pulse CP common control, takes the storage element withthe trigger. Nearly now all successions logic all is "the synchronizedlogic", some "the clock" the signal, all internal memories (internalcondition) only can in the clock border time change. In the successionlogic the most basic storage part is a trigger. The synchronized logic most main merit is it is very simple. In eachelectric circuit operation must have in the fixed gap to completebetween the clock two pulses, is called "the clock cycle". Underrefers has in this condition satisfies (did not consider other certaindetails), the electric circuit can guarantee is reliable. The synchronized logic also has two main characteristics: 1. clocks signals must have to distribute on the electric circuit eachtrigger. But the clock usually all is the high-frequency signal, thiscan cause the power the consumption, also has the quantity of heat.Even if each trigger has not handled any matter, also can consume thefew energies, therefore can cause the waste heat production. 2. biggest possible clocks frequencies are the slowest logical waydecided by the electric circuit in, also is the essential way. Themeaning is said each logical the operation, from is simplest complexto, all must in each time arteries cycle complete. One kind uses forto eliminate this kind of limit the method, is separates into thecomplex operation several simple operations, this kind of technologyis called "the assembly line". This kind of technology inmicroprocessor unusual remarkableness, uses for to help the promotionnowadays the processor clock frequency. The asynchronous succession logic circuit most basic storage part isthe latch, the latch may change its condition in any time, accordingto other latch signals changes, their new condition can produce.Asynchronous circuit complex along with logical gate increase, butcomplex also fast increase, therefore they majority of merely use inthe young application. However, the computer assistance graduallydesigns the tool to be allowed to simplify these work, permits a morecomplex design. My graduation thesis topic is "based on the ARM+FPGA Movement Controlcard Research", under I to discuss a document simple introduction, theclassical computer numerical control system (CNC, ComputerizedNumerical Control) generally uses the simulation voltage outputactuation servo unit, the computer simulation connection partiallinear discrete component many, the system space huge, the antijammingability is worse. Along with the digital circuit technology vigorousdevelopment, studies the entire digitized numerical control systemoneself after to become the inevitable tendency. This topic research uses the scene programmable gate array (FPGA,Field Programmable Gate Array) the integration rate high, the volumesmall, the low power loss, the redundant reliability, maycharacteristic and so on on-line revision, as well as using Verilogthe HDL language programming method, the design nimble, the revisionconvenient, the probability is good and so on the characteristic,designs the numerical control system the movement control chip. Thischip is the movement control card core are partial, can simultaneouslycontrol 4 servometers or step enters the motor the movement, it by thepulse string form output, can and step enters the motor to theservometer to carry on the position control and the speed control. The main work includes: (1) carries on the analysis to the numericalcontrol system research present situation, the determinationdevelopment pattern. (2) completes the overall system the hardwarecircuit design, the key point is the FPGA module design, theconfirmation, the revision and the stereotypia. (3) conducts theresearch to the S control curve, analyzes its type, determines itsfunction expression. (4) carries on the debugging to the main module,has produced the experimental result. (5) has carried on the summaryto the research content, has made the forecast to the movement controltechnology development. Has several technologies in the design processis the cost design key: Actuation pulse width and speed precision andfree integer frequency division technology and so on The design probably needs half year about the time tocomplete, in this half year, I has learned very many knowledge: Canhave the clear understanding to the NC axis control unit, can learn touse the EDA electron design tool, and could grasp FPGA and the VHDLknowledge, had in the independent development the small scaleintegration electric circuit ability, also had the profoundunderstanding to the large scale integrated circuit performancehistory.
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