Question

错误：在fenpin.v的Verilog HDL语法错误（127）文件的末尾附近;期待，或一个标识符，或“（”

急用！！实在是找不出错误，求高手指点

module fenpin(Clk,S1,D0,D1,D2,D3,D4,D5,clkout);

input Clk,S1;
output clkout;
output D0,D1,D2,D3,D4,D5;

reg clkout;
reg [31:0] Cout;
reg Clk_En;
reg i;
reg D0,D1,D2,D3,D4,D5;
wire S;

assign #4 S=S1;

always @(posedge S1)
begin
if (i == 3'b101)
i <= 3'b000;
else
i <= i + 3'b001;
end

always @(posedge Clk )
begin
case (i)
3'b000:begin
Cout <= (Cout == 32'd49)? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout== 32'd49)? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=1;
D1<=0;
D2<=0;
D3<=0;
D4<=0;
D5<=0;

end

3'b001: begin
Cout<= (Cout == 32'd490) ? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout == 32'd490) ? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=0;
D1<=1;
D2<=0;
D3<=0;
D4<=0;
D5<=0;

end

3'b010:begin

Cout <= (Cout == 32'd4900) ? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout == 32'd4900) ? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=0;
D1<=0;
D2<=1;
D3<=0;
D4<=0;
D5<=0;

end

3'b011: begin

Cout <= (Cout == 32'd49000) ? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout == 32'd49000) ? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=0;
D1<=0;
D2<=0;
D3<=1;
D4<=0;
D5<=0;

end

3'b100: begin

Cout <= (Cout == 32'd490_000) ? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout == 32'd490_000) ? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=0;
D1<=0;
D2<=0;
D3<=0;
D4<=1;
D5<=0;

end

3'b101:begin
Cout <= (Cout == 32'd49000_00) ? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout == 32'd49000_00) ? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=0;
D1<=0;
D2<=0;
D3<=0;
D4<=0;
D5<=1;

end

default : begin

Cout <= (Cout == 32'd50000_000) ? 32'd0 : (Cout + 32'd1);
Clk_En <= (Cout == 32'd50000_000) ? 1'd1 : 1'd0;
clkout<=Clk_En;
D0<=0;
D1<=0;
D2<=0;
D3<=0;
D4<=0;
D5<=0;
end
endcase

end

endmoudle

Answer 1

你的“endmoudle”应该是“endmodule”