Question

verilog编程，在quartus2下编译报错

`timescale 1ns/1ns
module counter(cnt,clk,data,rst,load);//Becareful the ';',and the module name must the same as source file name.
output [4:0]cnt;
input [4:0]data;
input clk,rst,load;
reg [4:0]cnt;

always@(rst)
begin
if(!rst)
#3 assign cnt=0;
else
deassign cnt;
end

always@(posedge clk)
begin
if(load)
cnt<=#3data;
else
cnt<=#4cnt+1;
end
endmodule

Error (10043): Verilog HDL unsupported feature error at counter.v(11): Procedural Continuous Assignment to register is not supported
过程性连续赋值对寄存器不支持，可是书上却说过程性连续赋值对寄存器和线网都支持，到底是怎么一回事啊？

Answer 1

　　assign用于连续赋值Continuous Assignment，只能付给net类型，若将assign用在了过程块中（initial，always）,则此时是过程连续赋值 Procedural Continuous Assignment，此时，它只支持寄存器。 以下是外国教材：
9.1 Procedural Continuous Assignments
　　We studied procedural assignments in , Procedural Assignments. Procedural assignments assign a value to a register. The value stays in the register until another procedural assignment puts another value in that register. Procedural continuous assignments behave differently. They are procedural statements which allow values of expressions to be driven continuously onto registers or nets for limited periods of time. Procedural continuous assignments override existing assignments to a register or net. They provide an useful extension to the regular procedural assignment statement.
9.1.1 assign and deassign
　　The keywords assign and deassign are used to express the first type of procedural continuous assignment. The left-hand side of procedural continuous assignments can be only be a register or a concatenation of registers. It cannot be a part or bit select of a net or an array of registers. Procedural continuous assignments override the effect of regular procedural assignments. Procedural continuous assignments are normally used for controlled periods of time.
　　A simple example is the negative edge-triggered D-flipflop with asynchronous reset that we modeled in . In , we now model the same D_FF, using assign and deassign statements.

Answer 2

改成这样就好了
always @(posedge clk or negedge rst)
if(!rst) cnt<=5'd0;
else if(load) cnt<=data;
else cnt<=cnt+5'd1;
学verilog语法看夏宇闻的《Verilog数字系统设计教程（第二版）》。

Answer 3

在过程块中不能用连续赋值语句对reg类型赋值。
你的cnt是reg类型，为什么还要用assign呀。而且是在过程语句中。
assign是用来给wire型赋值的。

http://zhidao.baidu.com/question/323551680.html
你们认识么。一模一样的。。。

追问

不认识，我是按照书上的代码敲的，这书坑爹了。书上说过程性连续赋值语句，可以给reg型也可以给wire型赋值，这句话错了吗？

追答

不知道是什么书。
连续赋值一般给wire
过程块一般给reg
反正assign肯定是不能在过程块中出现的。看英文书吧，呵呵。

追问

谢谢你了，我问了老师，老师用xlinx ise编译这段程序没有问题，他说quartus2对Verilog的支持程度没有ise好。

Answer 4

0.0