Question

quartus verilog 程序 我在在书上练习的时候老出现这样的错误

module compare(equal,a,b);
input a,b;
output equal;
assign equal=(a==b)?1:0;
endmodule

'timescale 1ns/1ns;
'include "./compare.v"

module test;
reg a,b;
wire equal ;
initial
begin
a=0;
b=0;
#100 a=0; b=1;
#100 a=1; b=1;
#100 a=1; b=0;
#100 a=0; b=0;
#100 $stop;
end
compare m(.equal(equal),.a(a),.b(b));
endmodule

这是夏宇闻教授verilog 314页的练习
错误情况如下：
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Error (10170): Verilog HDL syntax error at test.v(8) near text '
Error (10112): Ignored design unit "compare" at test.v(1) due to previous errors
Error (10170): Verilog HDL syntax error at test.v(8) near text "'"; expecting an identifier, or "module", or "macromodule", or "function", or "parameter", or "primitive", or "real", or "realtime", or "reg", or "specparam", or "task", or "time", or "integer", or "config", or "localparam", or "(*", or "include", or "library"
Info: Found 0 design units, including 0 entities, in source file test.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 169 megabytes
Error: Processing ended: Tue Apr 12 17:18:20 2011
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:01
请指教

Answer 1

这里是两个程序，可以在modelsim里分别编写、仿真，就可以看出波形图来验证程序
要是在QUartus上，只要写下面这个程序就可以了，然后编译，应该不会有错。
module compare(equal,a,b);
input a,b;
output equal;
assign equal=(a==b)?1:0;
endmodule

Answer 2

两个module中间插入这样的语句？应该是两个文件吧。
另外
'timescale 1ns/1ns;
'include "./compare.v"
检查分号还有这个compare.v文件是什么情况。
另外注意【标号`】 (数字1左边按键)和【标号'】（双引号按键）的区别，请检查书本上关于timescale语句的说明。