Question

QuartusII编译错误Error: Can't implement PLL as Cyclone II PLL type

Audio_PLL 模块是使用锁相环产生的一个频率为18.409091MHz 的时钟信号，工程编译时出现如下的错误，为什么？
Error: Can't implement PLL "Audio_PLL:p1|altpll:altpll_component|pll" as Cyclone II PLL type
Error: Can't implement clock multiplication and clock division parameter values for PLL "Audio_PLL:p1|altpll:altpll_component|pll"
Error: Can't implement PLL because Division and Multiplication cannot be achieved
Info: Implementing clock multiplication of 15, clock division of 22, and phase shift of 0 degrees (0 ps) for Audio_PLL:p1|altpll:altpll_component|_clk0 port

Answer 1

生成模块时参数设置错误，应按照clock multiplication of 15, clock division of 22来设置就好。