Question

用VHDL语言写数字钟，要有整点报时的

设计任务：
1、能进行正常的时、分、秒计时功能，分别由6只数码管显示24
小时、60分、60秒。
2、按下试验箱上的某个按键时，计时器迅速递增，并按24小时
循环，计到23小时后再回到00。
3、按下试验箱上的某个按键时，计分器迅速递增，并按60分循
环，计到59分后再回到00。
4、利用试验箱上的扬声器可以实现整点报时功能，当计时到达
59分50秒时开始报时，在59分50秒、52秒、54秒、56秒、
58秒时鸣叫，鸣叫声频率为500HZ，整点报时频率可定义为
1KHZ.

具体时间用6位数码管来显示，具有整点报时
功能.

答案发到我邮箱就行了，906456725@qq.com

Answer 1

发给你了。。。。。

Answer 2

a.秒计数器设计（xsecond）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity xsecond is
port (clk:in std_logic;
clkset:in std_logic;
setmin:in std_logic;
reset:in std_logic;
secout:out std_logic_vector(6 downto 0);
enmin:out std_logic );
end xsecond;
architecture xsecond_arch of xsecond is
signal sec:std_logic_vector(6 downto 0);
signal emin:std_logic;
signal secl: std_logic;
begin
process (reset,sec,emin,setmin,clkset)
begin
if reset='0' then
enmin<='0';
secout<="0000000";
secl<='1';
else
secl<='0';
secout<=sec;
if clkset='1'and clkset'event then
if setmin ='0'then
enmin <='1';
else
enmin<=emin;
end if;
end if;
end if;
end process;
process(clk,secl)
alias lcount: std_logic_vector(3 downto 0)is sec (3 downto 0);
alias hcount:std_logic_vector(2 downto 0)is sec (6 downto 4);
begin
if secl='1' then
sec<="0000000";
else
if (clk='1' and clk'event) then
if lcount <=9 then
lcount<="0000";
if hcount/=5 then
hcount <=hcount+1;
emin<='0';
else
hcount<="000";
emin<='1';
end if;
else
lcount<=lcount+1;
emin<='0';
end if;
end if;
end if;
end process;
end xsecond_arch;
b.分计数器设计（xminute）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity xminute is
port (clkmin:in std_logic;
clk:in std_logic;
sethour:in std_logic;
reset:in std_logic;
minout:out std_logic_vector(6 downto 0);
enhour:out std_logic );
end xminute;
architecture xminute_arch of xminute is
signal min:std_logic_vector(6 downto 0);
signal ehour:std_logic;
signal minl: std_logic;
begin
process (reset,clk,min,sethour,ehour)
begin
if reset='0' then
enhour<='0';
minout<="0000000";
minl<='0';
else
minl<='1';
minout<=min;
if clk='1'and clk'event then
if sethour ='0'then
enhour <='1';
else
enhour<=ehour;
end if;
end if;
end if;
end process;
process(clkmin,minl)
alias lcountm: std_logic_vector(3 downto 0)is min (3 downto 0);
alias hcountm:std_logic_vector(2 downto 0)is min (6 downto 4);
begin
if minl='0' then
min<="0000000";
else
if (clkmin='1' and clkmin'event) then
if lcountm <=9 then
lcountm<="0000";
if hcountm/=5 then
hcountm <=hcountm+1;
ehour<='0';
else
hcountm<="000";
ehour<='1';
end if;
else
lcountm<=lcountm+1;
ehour<='0';
end if;
end if;
end if;
end process;
end xminute_arch;
c.时计数器设计（xhour）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity xhour is
port (clkhour:in std_logic;
reset:in std_logic;
hourout:out std_logic_vector(5 downto 0));
end xhour;
architecture xhour_arch of xhour is
signal hour:std_logic_vector(5 downto 0);
begin
process (reset,clkhour,hour)
alias lcount: std_logic_vector(3 downto 0)is hour(3 downto 0);
alias hcount:std_logic_vector(1 downto 0)is hour(5 downto 4);
begin
if reset='0' then
hourout<="000000";
hour<="000000";
else
if (clkhour='1' and clkhour'event) then
if lcount <=9 then
lcount<="0000";
hcount<=hcount+1;
else
if hour="100011" then
hour<="000000";
else
lcount<=lcount+1;
end if;
end if;
end if;
hourout<=hour;
end if;
end process;
end xhour_arch;
d.动态扫描电路设计（xsettime）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity xsettime is
port (hour:in std_logic_vector(5 downto 0);
min:in std_logic_vector(6 downto 0);
sec:in std_logic_vector(6 downto 0);
reset : in std_logic;
clk:in std_logic;
sel:out std_logic_vector(2 downto 0);
d_out:out std_logic_vector(3 downto 0));
end xsettime;
architecture xsettime_arch of xsettime is
signal sel1:std_logic_vector(2 downto 0);
begin
process (reset,sec,min,hour,clk,sel1)
begin
if reset='0' then
sel <="000";
d_out<="0000";
sel1<="000";
else
if(clk='1'and clk'event) then
if sel1<5 then
sel1<=sel1+1;
else
sel1<="000";
end if;
end if;
sel<=sel1;
case sel1 is
when "000"=>
d_out( 3 )<='0';
d_out( 2 )<='0';
d_out( 2 )<=hour( 5 );
d_out( 0 )<=hour( 4);
when "001"=>
d_out <= hour(3 downto 0);
when "010"=>
d_out( 3 )<='0';
d_out( 2 )<=min( 6 );
d_out( 1 )<=min( 5);
d_out( 0 )<=min( 4);
when "011"=>
d_out <= min(3 downto 0);
when "100"=>
d_out( 3 )<='0';
d_out( 2 )<=sec( 6 );
d_out( 1 )<=sec( 5);
d_out( 0 )<=sec( 4);
when "101"=>
d_out <= sec(3 downto 0);
when others=>
null;
end case;
end if;
end process;
end xsettime_arch;
e.报时电路设计（xalert）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity xalert is
port (clk:in std_logic;
d_in:in std_logic_vector(6 downto 0);
speak : out std_logic;
d_out:out std_logic_vector(2 downto 0) );
end xalert;
architecture xalert_arch of xalert is
type state is (s1,s2,s3,s4);
signal next_state,current_state:state;
begin
process (clk,current_state,d_in)
begin
if d_in/="0000000" then
speak <='0';
next_state <=s1;
current_state<=s1;
d_out<="000";
else
if clk='1'and clk'event then
speak <='1';
end if;
case current_state is
when s1 =>
d_out<="000";
next_state<=s2;
when s2 =>
d_out<="001";
next_state<=s3;
when s3 =>
d_out<="010";
next_state<=s4;
when s4 =>
d_out<="100";
next_state<=s1;
when others =>
d_out<="000";
null;
end case;
end if;
end process;
end xalert_arch;