Question

使用Verilog HDL实现50MHz分频为20MHz有完整程序

Answer 1

加了端口定义，再试试。

module clk_20m_div(clk_50m,clk_20m, rst);
input clk_50m,rst;
output reg clk_20m;
reg [2:0] cnt;
always@(posedge clk_50m)
if(!rst)
cnt <= 3'b0;
else if (cnt >= 3'h4)
cnt <= 3'b0;
else
cnt <= cnt + 1'b1;
always@(posedge clk_50m)
if(!rst)
clk_20m <= 1'b0;
else if (cnt == 3'h1)
clk_20m <= 1'b1;
else if (cnt == 3'h4)
clk_20m <= 1'b0;
endmodule