Question

verilog 问题

module FA_Str(A,B,Cin,Sum,Cout);
input A,B,Cin;
output Sum,Cout;
wire S1,T1,T2,T3;
xor
X1(S1,A,B),
X2(Sum,S1,Cin);
and
A1(T3,A,B),
A2(T2,B,Cin),
A3(T1,A,Cin);
or
O1(Cout,T1,T2,T3);
endmodule
module Eightbitadder(FA,FB,FSum,FCout);
input [8:1] FA,FB;
output [8:1] FSum;
input FCout;
wire [1:7] FTemp;
FA_Str
FA1(FA[1], FB[1], 0, FSum[1], FTemp[1]),
FA2(FA[2], FB[2], FTemp[1], FSum[2], FTemp[2]),
FA3(FA[3], FB[3], FTemp[2], FSum[3], FTemp[3]),
FA4(FA[4], FB[4], FTemp[3], FSum[4], FTemp[4]),
FA5(FA[5], FB[5], FTemp[4], FSum[5], FTemp[5]),
FA6(FA[6], FB[6], FTemp[5], FSum[6], FTemp[6]),
FA7(FA[7], FB[7], FTemp[6], FSum[7], FTemp[7]),
FA8(FA[8], FB[8], FTemp[7], FSum[8], FTemp[8]);
endmodule

Error (10228): Verilog HDL error at Verilog2.v(1): module "FA_Str" cannot be declared more than once
Info (10499): HDL info at 8bitadder.v(17): see declaration for object "FA_Str"
Error (10112): Ignored design unit "Eightbitadder" at Verilog2.v(15) due to previous errors
Info: Found 0 design units, including 0 entities, in source file verilog2.v
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 271 megabytes
Error: Processing ended: Sat May 24 21:48:57 2014
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings
是什么问题，初学者，求教

Answer 1

你是不是错误提示：Error (10200): Verilog HDL Conditional Statement error at ……: cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
这是因为，你的“always@(posedge clk or negedge r_est)”表明在clk上升沿或r_est下降沿这两个敏感事件发生时always语句块得以触发；而always中的if条件语句必须至少有一个条件指向其中一个敏感事件（边界标识符）；所以写成“if（r_est)...else...”就会出错。

你可以把“always@(posedge clk or negedge r_est)”改为“always@(posedge clk or posedge r_est)”再编译试试，应该就没问题了。

你右键该错误点击“Help”里是这么说的：
CAUSE: In a conditional statement at the specified location in a Verilog Design File (.v), you specified a condition that Quartus II Integrated Synthesis cannot use to classify the edges in the enclosing always construct's event control. When an event control contains multiple edges, Quartus II Integrated Synthesis distinguishes the asynchronous control signals from the clock by analyzing the conditional statements in the always construct. For example, the following code fragment contains an always construct whose event control contains three edges---two asynchronous resets and a clock.
always @ (posedge clk or posedge rst1 or posedge rst2)
begin
if ( rst1 || rst2 )
q <= 1'b0;
else
q <= d;
end
Quartus II Integrated Synthesis uses the if condition to identify the two asynchronous resets and, by implication, the clock. For edge classification, Quartus II Integrated Synthesis requires that a condition fall into one of two categories. It can refer to a single edge identifier (to match posedge events) or its complement (to match negedge events), for example, rst1, !rst1, rst1 == 1'b1, rst1 == 1'b0. It can also OR two or more expressions that each refer to a single edge identifier or its complement, for example, (rst1 || rst2), (!rst1 || !rst2).
You can receive this error if your condition tests for the wrong polarity, or if it tests for the value of a variable that is not an edge in the event control. For example, to match a posedge rst event, the condition must be rst or rst = 1'b1.
Finally, you can receive this error if you are attempting to use a single condition expression to test for both an asynchronous reset/set and a synchronous reset/set condition. The following code fragment contains an example of an illegal condition expression:
always @ (posedge clk or posedge rst)
begin
if ( rst || sync_rst )
q <= 1'b0;
else
q <= d;
end
Quartus II Integrated Synthesis generates this error message when compiling this design because it cannot match sync_rst to an edge on the sensitivity list.

其中关键的语句我摘译一下，不一定译得准确，不过大体意思我想你应该可以了解了：
原因：……指定了一个条件，Quartus II 综合器不能够将该条件用于在封闭的always结构的事件控制中对边界进行区分。当一个事件控制中包含多重边界，Quartus II 综合器通过分析always结构中的条件语句来对时钟和异步控制信号加以区分。……
Quartus II 综合器采用if条件来鉴别两个异步reset信号，并隐含地鉴别了clock信号。为了分类的需要，Quartus II 综合器需要有一个条件落入两个类别之一。它可以指向一个单独的边界标识符（以匹配posedge事件）或它的补语（以匹配negedge事件），例如， rst1, !rst1, rst1 == 1'b1, rst1 == 1'b0。它也可以是OR两个或更多的表达式，其中每一个指向一个单独的边界标识符或它的补语……
当你的条件测试发现错误极性，或者它测试变量的值，但该值在事件控制中并不是一个边界时，你会接到这个错误。例如，为了匹配一个posedge rst事件，条件必须是rst或rst = 1'b1。

编译错误时多看看Help，讲得很详细~

追问

额，我没有用always

Answer 2

我也遇到同样的错误，最后发现是后面的 if 前面忘了加 else ！
写C语言习惯了。