Question

音调发生模块的verilog hdl源程序(简易电子琴的设计)

这是EDA技术实验与课程设计里的作业，谁有没明源程序啊，给个问题补充  2010-06-30 22:20谁有没有这个音调发生模块的verilog hdl源程序啊问题补充  2010-06-30 23:11VHDL源程序(TONE.VHD)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY TONE IS    PORT (INDEX:    IN STD_LOGIC_VECTOR(7 DOWNTO 0);          CODE:     OUT STD_LOGIC_VECTOR(6 DOWNTO 0);          HIGH:      OUT STD_LOGIC;          TONE0:     OUT INTEGER RANGE 0 TO 2047);END TONE;ARCHITECTURE ART OF TONE IS  BEGIN  SEARCH : PROCESS(INDEX)BEGINCASE INDEX IS    WHEN "00000001"=>TONE0 <=773;CODE<="1001111";HIGH<='1';WHEN "00000010"=>TONE0 <=912;CODE<="0010010";HIGH<='1';WHEN "00000100"=>TONE0 <=1036;CODE<="0000110";HIGH<='1';WHEN "00001000"=>TONE0 <=1116;CODE<="1001100";HIGH<='1';WHEN "00010000"=>TONE0 <=1197;CODE<="0100100";HIGH<='1';WHEN "00100000"=>TONE0 <=1290;CODE<="0100000";HIGH<='0';WHEN "01000000"=>TONE0 <=1372;CODE<="0001111";HIGH<='0';WHEN "10000000"=>TONE0 <=1410;CODE<="0000000";HIGH<='0';WHEN OTHERS =>TONE0<=2047;CODE<="0000001";HIGH<='0';    END CASE;  END PROCESS;END ART;问题补充  2010-07-01 00:10

Answer 1

说要求，输入输出，几个模块等等。