Question

verilog8位并行输入串行输出移位寄存器程序

Answer 1

input clk;
input rst;
input [7:0] data_in;
output [7:0] data_out;

reg [7:0] data;

wire data_out;

always @ (posedge clk or negedge rst)
if (~rst)
data <= data_in;
else
data <= data<<1; // 此处先移高位，后低位； 如果先低后高改为：data <= data>>1;

assign data_out = data[7]; // 此处先移高位，后低位； 如果先低后高改为：data[0]