Question

我想用ISE 中的SPARTAN-6芯片写一个全局时钟，PLL的，输入100MHz，输出10M，我想用它的IP_core

如何调用，如何例化到程序中。我只想让它输出10M 我用示波器观察。请给个使用说明或直接给程序。发邮箱fty932810@163.com

Answer 1

spartan6里面虽然含有独立的PLL和DCM，但是已经不直接支持你通过IPcore独立的使用了，取而代之是叫做“Clocking Wizard”，它帮你决定是用pll还是dcm还是全用。
如果你执意用pll，只能通过原语，pll原语如下：
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(1), // Multiply value for all CLKOUT clock outputs (1-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
.CLKIN_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30
// MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
.CLKOUT0_DIVIDE(1),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
.DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52)
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
.RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE
)
PLL_BASE_inst (
.CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock input
.CLKIN(CLKIN), // 1-bit input: Clock input
.RST(RST) // 1-bit input: Reset input
);

// End of PLL_BASE_inst instantiation
请确定你的需求再联系

追问

那如果我们就用DCM，不用锁相环，输入100M 输出在1M以下，这样可以吗？对了，还有，能用VHDL 语言吗？我比较熟悉VHDL 。谢谢

追答

输入100M 输出在1M以下 这个xilinx 的dcm是不支持的，分频最大支持16倍。
dcm原语的的vhdl是有的：

DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DSS_MODE => "NONE",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"c080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLK0 => CLK0,
CLK2X180 => CLK2X180
CLKDV => CLKDV, -- 1-bit output: Divided clock output
CLKFX => CLKFX, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => CLKFX180, -- 1-bit output: 180 degree CLKFX output
LOCKED => LOCKED, -- 1-bit output: DCM_SP Lock Output
PSDONE => PSDONE, -- 1-bit output: Phase shift done output
STATUS => STATUS, -- 8-bit output: DCM_SP status output
CLKFB => CLKFB, -- 1-bit input: Clock feedback input
CLKIN => CLKIN, -- 1-bit input: Clock input
DSSEN => DSSEN, -- 1-bit input: Unsupported, specify to GND.
PSCLK => PSCLK, -- 1-bit input: Phase shift clock input
PSEN => PSEN, -- 1-bit input: Phase shift enable
PSINCDEC => PSINCDEC, -- 1-bit input: Phase shift increment/decrement input
RST => RST -- 1-bit input: Active high reset input
);

有删减。
其中
CLKDV_DIVIDE => 2.0是分频数，最多到16倍

追问

也就是说只能把100M16分频 是吧！谢谢您的帮助。