Question

如何用verilog将50MHz分频到50kHz？

module cutlock(clock, clock—devide...之类的)

Answer 1

module cutclk( input clk,reset,
output reg clk_divide);
reg [9:0] clk_cnt;
always @(posedge clk or posedge reset)
if(reset)
begin
clk_cnt <= 10'd0;
clk_divide <= 0;
end
else if (clk_cnt == 10'd0)
begin
clk_cnt <= 10'd1;
clk_divide <= ~ clk_divide;
end
else if (clk_cnt == 10'd500)
begin
clk_cnt <=10'd1;
clk_divide <= ~ clk_divide;
end
else clk_cnt <= clk_cnt + 10'd1;

endmodule