Question

vhdl问题

我做这个课题遇到好多警告,请各位帮小弟看看,怎么解决,先谢了~~
Warning (10541): VHDL Signal Declaration warning at dfre.

vhd(28): used implicit default value for signal "keepcou3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.

Warning (10036): Verilog HDL or VHDL warning at dfre.vhd(29): object "ttclk" assigned a value but never read

Warning (10036): Verilog HDL or VHDL warning at dfre.vhd(30): object "ttsig" assigned a value but never read

Warning (10492): VHDL Process Statement warning at dfre.vhd(161): signal "clklk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list

Warning (10492): VHDL Process Statement warning at dfre.vhd(161): signal "testsignal" is read inside the Process Statement but isn't in the Process Statement's sensivitity list

Warning (10492): VHDL Process Statement warning at dfre.vhd(162): signal "testsignal" is read inside the Process Statement but isn't in the Process Statement's sensivitity list

Warning (10492): VHDL Process Statement warning at dfre.vhd(162): signal "enfre" is read inside the Process Statement but isn't in the Process Statement's sensivitity list

Warning (10492): VHDL Process Statement warning at display.vhd(15): signal "indata" is read inside the Process Statement but isn't in the Process Statement's sensivitity list

Warning: Reduced register "flag[2]" with stuck data_in port to stuck value GND

Warning: Reduced register "flag[0]" with stuck data_in port to stuck value VCC

Warning: Output pins are stuck at VCC or GND

Warning: Design contains 1 input pin(s) that do not drive logic

Warning: Following 23 pins have nothing, GND, or VCC driving

datain port -- changes to this connectivity may change fitting results
Warning: Found pins functioning as undefined clocks and/or memory enables

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
谢谢啊，可是我该怎么解除呢～！！

Answer 1

把你的原始程序发给我我给你看看！
W842702@163.COM

Answer 2

Warning (10541)的意思是设计中使用了一个未赋值的信号，并且没有复位值，这样该信号为无效值(确定但不可知)，被其他逻辑使用也许会导致错误。
Warning (10036)不用管它，大概是说有个信号未被使用，这样不会对逻辑产生任何影响，当然也可以考虑删除它。
Warning (10492)是很常见的，这个关系到编码风格问题。在process里作为被判断信号(if或者case后面的)或者赋值语句右端信号通常应该写在process的敏感信号表里。有些eda工具不检查这个，可能会导致仿真结果与综合出来的电路不一致。实际上，综合工具在综合的时候会自动把这类信号添加到敏感信号表里，但仿真工具不会，而是完全按照代码体现的语意来仿真。
Reduced register ...这两个应该是说明eda工具所作的优化，去掉了一些多余的D触发器。
Output pins are stuck at VCC or GND 如果正是希望某些输出被固定置高电平或低电平或者无所谓，就不用管它，否则请检查代码。
Design contains 1 input pin(s) that do not drive logic 这个也比较常见，eda工具会提醒设计中没被用到的输入，然而这经常就是设计者的本意(不关心某些输入)。
Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew 这就是说明门控时钟带来的扭曲
另外两个不太清楚 应该是和设计的具体实现有关