Question

求程序：用vhdl语言编写出20进制计数器并在数码管上显示出来

Answer 1

计数模块

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity count20 is
port(clk:in std_logic;
out1a,out1b,out2a,out2b:out std_logic_vector (7 downto 0):="00000000"
);
end count20;

architecture Behavioral of count20 is
component disp is
port(clk:in std_logic;
input: integer range 0 to 19:=0;
output1:out std_logic_vector(7 downto 0):="00000000";
output2:out std_logic_vector(7 downto 0):="00000000"
);
end component;
signal temp1,temp2:integer range 0 to 19:=0;
begin
process(clk)
begin
if clk'event and clk='1' then
if temp1=19 then
if temp2=19 then
temp1<=0;temp2<=0;
else
temp2<=temp2+1;temp1<=0;
end if;
else temp1<=temp1+1;
end if;
end if;
end process;
u1:disp port map(clk,temp1,out1a,out1b);
u2:disp port map(clk,temp2,out2a,out2b);
end Behavioral;显示模块，不知道你是用的什么数码管我用的8段共阴
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity disp is
port(clk:in std_logic;
input: integer range 0 to 19:=0;
output1:out std_logic_vector(7 downto 0):="00000000";
output2:out std_logic_vector(7 downto 0):="00000000"
);
end disp;

architecture Behavioral of disp is

begin
process(clk)
begin
case input is
when 0 =>output1<="00000000";output2<="00000000";
when 1 =>output1<="01100000";output2<="00000000";
when 2 =>output1<="11011010";output2<="00000000";
when 3 =>output1<="11110010";output2<="00000000";
when 4 =>output1<="01100110";output2<="00000000";
when 5 =>output1<="11011010";output2<="00000000";
when 6 =>output1<="10111110";output2<="00000000";
when 7 =>output1<="11100000";output2<="00000000";
when 8 =>output1<="11111110";output2<="00000000";
when 9 =>output1<="11110110";output2<="00000000";
when 10=>output1<="00000000";output2<="01100000";
when 11=>output1<="01100000";output2<="01100000";
when 12=>output1<="11011010";output2<="01100000";
when 13=>output1<="11110010";output2<="01100000";
when 14=>output1<="01100110";output2<="01100000";
when 15=>output1<="11011010";output2<="01100000";
when 16=>output1<="10111110";output2<="01100000";
when 17=>output1<="11100000";output2<="01100000";
when 18=>output1<="11111110";output2<="01100000";
when 19=>output1<="11110110";output2<="01100000";
when others =>output1<="00000001";output2<="00000001";
end case;
end process;
end Behavioral;