Question

在线等 如何运用用VHDL语言设计一个二分频器

如何语言运用VHDL语言设计一个二分频器 请写得详细些 谢谢了哈

Answer 1

以前的。。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin isport(clk:in std_logic;
m_clk:out std_logic);architecture one of fenpin issignal fp:std_logic_vector(1downto 0);begin
process(clk)
begin
if rising_edge(clk) then
if fp<2 then
fp<=fp+1;
else
fp<="00";m_clk<=not m_clk;
end if;
end if;
end process;end;大概是这样的吧，没有验证。。。看要几分频的改下fp的位数，还有对应的“fp<几分频”就可以了。m_clk所得的波形就是你要的了。

Answer 2

Library ieee;
Use ieee.std_logic_1164.all;
Entity moore is
Port(clk: in std_logic;
Reset: in std_logic;
clk0: buffer std_logic;
Din: in std_logic;
Dout: out std_logic_vector(0 to 2) );
End moore;
architecture a of moore is
Type state_type is (s0, s1, s2 );
Signal state :state_type;
beginfenpin_state: Process(clk)
variable cnt1: integer range 0 to 4999999;
variable x1: std_logic:='0';
begin
if clk' event and clk='1' then
if cnt1<4999999 then
cnt1:=cnt1+1;
else
cnt1:=0;
x1:=not x1;
end if;
end if;
clk0<=x1;
end process;你仿真的时候把499999改成小数字，4,8，都行