Question

谁知道Verilog 中的posedge用法是什么？为什么有这两个错误？

always @(posedge clk_1M) begin
if(count1>=20000 or posedge THR) //待测信号THR上升沿count1=0
count1 <= 0;
else begin
count1 <= count1 + 1;
end
end
always @(negedge THR) begin
width1 <= count1;
det1 <= width1-1000;//THR宽度变化量
end
有
Error (10170): Verilog HDL syntax error at four_pass.v(80) near text "or"; expecting ")"
Error (10170): Verilog HDL syntax error at four_pass.v(82) near text "else"; expecting "end"
两个错误为什么啊？求大神帮助。

Answer 1

你那样写有语法错误很正常啊，posedge一般都用于always @（）的括号内，表示THR的上升沿到来时，运行always快内的程序，你如果需要用到THR的上升沿来作为判断条件，建议你这样写代码：
reg THR1;
reg THR2;
always @ ( posedge clk_1M or negedge reset_n )
if( !reset_n )
begin
THR1 <= 1'b0;
THR2 <= 1'b0;
end
else
begin
THR1 <= THR;
THR2 <= THR1;
end
always @( posedge clk_1M )
if( count1>=20000 || ( THR1 && !THR2 ) )
count1 <= 0;
else
count1 <= count1 + 1;