Question

verilog中定义了一系列关键字，它们有哪些

Answer 1

网上找一个verilog的wordfile，里面列出了能引起verilog语法高亮的所有词。下面贴的是system verilog的关键词。现在所有仿真工具也都支持system verilog，所以下面所有词都有特殊意义了
alias always always_comb always_ff always_latch and assert assign assume automatic
before begin bind bins binsof bit break buf bufif0 bufif1 byte
case casex casez cell chandle class clocking cmos config const constraint context continue cover covergroup coverpoint cross
deassign default defparam design disable dist do
edge else end endcase endclass endclocking endconfig endmodule endgroup endfunction endgenerate endinterface endmodule endpackage
endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event expect export extends extern
final first_match for force forever fork forkjoin function
generate genvar
highz0 highz1
if iff ifnone ignore_bins illegal_bins import incdir include initial inout input inside instance int interface integer intersect
join join_any join_none
large liblist library local localparam longint
macromodule matches medium modport module
nand negedge new nmos none nor noshowcancelled not notif0 notif1 null
or output
package packed parameter pulsestyle_onevent pulsestyle_ondetect pmos posedge primitive priority program property protected pull0 pull1 pullup pulldown pulsestyle_onevent pulsestyle_ondetect pure
rand randc randcase randsequence randomize real realtime ref reg release return repeat rcmos rnmos rpmos rtran rtranif0 rtanif1
scalared sequence showcancelled shortint shortreal signed small solve specify specparam static strength string strong0 strong1 struct super supply0 supply1
table tagged task this time timeprecision timeunit tran tranif0 tranif1 tri tri1 tri0 triand trior trireg throughout type typedef
union unique unsigned use uwire
var vectored virtual void
wait wait_order wand weak0 weak1 while wildcard with within wire wor
xnor xor