Question

关于VHDL的错误

我检查了即便没有错误，是按课本的报告写得，可是还是出错
library ieee;
use ieee.std_logic_1164.all;
entity mux3 is
port(in1,in2,in3,in4 : in std_logic_vector(2 downto 0);
sel : in std_logic_vector(1 downto 0);
out1 : out std_logic_vector(2 downto 0));
end mux3;
architecture arc_mux of mux3 is
begin
process(in1,in2,in3,in4.sel)
begin
case sel is
when "00"=>out1<=in1;
when "01"=>out1<=in2;
when "10"=>out1<=in3;
when "11"=>out1<=in4;
when others=>out1<="XXXX";
end case;
end process;
end arc_mux;

没法截图，这是底下的错误重点是前三句
Error (10448): VHDL error at /MUX3.vhd(10): record type std_logic_vector is used but not declared
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 207 megabytes
Error: Processing ended: Thu Sep 11 09:32:10 2014
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
有时候我弄完了第一个文件，再弄第二个时，左上角的蓝色插头仍显示第一个文件的名称，这时再编译总是出粗是什么情况？？？？？？？？

Answer 1

process(in1,in2,in3,in4.sel) 这里面的"点"应该是“逗号” 估计是你抄错了吧

Answer 2

把常用的几个包都加上，
比如USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

Answer 3

端口声明“port(int1,int2 : in bit_vector; pout : out bit_vector);”中的bit_vector没有指明数组下标的范围。

追问

那要怎么改，具体点，你打的啥啊