Question

怎么将25mhz用分频器分成100hz用verilog语言实现

怎么将25mhz用分频器分成100hz用verilog语言实现

Answer 1

你写一个计数器 计数到125000时计数器清零 并且clk_div翻转

Answer 2

always@(posedge clk)
begin
if(rst == 1'b1)
begin
divider <= 0;
clk_100 <= 0;
end
else if(divider == 125000)
begin
divider <= 0;
clk_100 <= ~clk_100;
end
else
begin
divider <= divider + 1;
end
end

Answer 3

不就是设计个计数器吗？