Question

求一个Verilog编写的交通灯显示模块程序，要求：东西，南北各一个灯，红30s，绿25s，黄5s，循环！

Answer 1

module TSPT_LIT(
input sys_clk ,
input sys_rst_n,
output reg [1:0] man_s2n , //人行南北
output reg [1:0] man_e2w , //人行东西
output reg [1:0] car_s2n , //车行南北
output reg [1:0] car_e2w , //车东西
output reg [1:0] car_s2w , //车南北左转
output reg [1:0] car_e2s //车东西左转
);

parameter [7:0] ST_TIME = 8'd50 ; //直行时间
parameter [7:0] TL_TIME = 8'd20 ; //左转时间
parameter [7:0] YL_TIME = 8'd6 ; //黄灯时间

reg [7:0] st_count ;
reg [7:0] tl_count ;
reg [7:0] yl_count ;

reg [3:0] c_state ;
reg [3:0] n_state ;
//状态机9种状态
parameter [3:0]idel = 4'd0 ;
parameter [3:0]s2n_green = 4'd1 ;
parameter [3:0]s2n_yellow = 4'd2 ;
parameter [3:0]s2w_green = 4'd3 ;
parameter [3:0]s2w_yellow = 4'd4 ;
parameter [3:0]e2w_green = 4'd5 ;
parameter [3:0]e2w_yellow = 4'd6 ;
parameter [3:0]e2s_green = 4'd7 ;
parameter [3:0]e2s_yellow = 4'd8 ;

always @(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n) c_state <= idel ;
else c_state <= n_state;
end

always @(*) begin
case(c_state)
idel:
begin
n_state <= s2n_green ;
end
s2n_green:
begin
if(st_count==ST_TIME)
n_state <= s2n_yellow ;
else
n_state <= s2n_green ;
end
s2n_yellow:
begin
if(yl_count==YL_TIME)
n_state <= s2w_green ;
else
n_state <= s2n_yellow ;
end
s2w_green:
begin
if(tl_count==TL_TIME)
n_state <= s2w_yellow ;
else
n_state <= s2w_green ;
end
s2w_yellow:
begin
if(yl_count==YL_TIME)
n_state <= e2w_green ;
else
n_state <= s2w_yellow ;
end
e2w_green:
begin
if(st_count==ST_TIME)
n_state <= e2w_yellow ;
else
n_state <= e2w_green ;
end
e2w_yellow:
begin
if(yl_count==YL_TIME)
n_state <= e2s_green ;
else
n_state <= e2w_yellow ;
end
e2s_green:
begin
if(tl_count==TL_TIME)
n_state <= e2s_yellow ;
else
n_state <= e2s_green ;
end
e2s_yellow:
begin
if(yl_count==YL_TIME)
n_state <= s2n_green ;
else
n_state <= e2s_yellow ;
end
default :
begin
n_state <= idel ;
end
endcase
end

always @(*) begin
case(c_state)
idel:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd0 ;
end
s2n_green:
begin
man_s2n <= 2'd1 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd1 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd0 ;
end
s2n_yellow:
begin
man_s2n <= 2'd1 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd2 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd0 ;
end
s2w_green:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd1 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd0 ;
end
s2w_yellow:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd2 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd0 ;
end
e2w_green:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd1 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd1 ;
car_e2s <= 2'd0 ;
end
e2w_yellow:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd1 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd2 ;
car_e2s <= 2'd0 ;
end
e2s_green:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd1 ;
end
e2s_yellow:
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd2 ;
end
default :
begin
man_s2n <= 2'd0 ;
man_e2w <= 2'd0 ;
car_s2n <= 2'd0 ;
car_e2w <= 2'd0 ;
car_s2w <= 2'd0 ;
car_e2s <= 2'd0 ;
end
endcase
end

always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) st_count <= 8'd0 ;
else begin
if(c_state == s2n_green || c_state == e2w_green)
st_count <= st_count + 8'b1 ;
else
st_count <= 8'b0 ;
end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) yl_count <= 8'd0 ;
else begin
if(c_state == s2n_yellow || c_state == e2w_yellow || c_state == s2w_yellow || c_state == e2s_yellow)
yl_count <= yl_count + 8'b1 ;
else
yl_count <= 8'b0 ;
end
end

always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) tl_count <= 8'd0 ;
else begin
if(c_state == s2w_green || c_state == e2s_green)
tl_count <= tl_count + 8'b1 ;
else
tl_count <= 8'b0 ;
end
end

endmodule

需要改时间的话改paramater的参数吧