Question

VHDL怎么实现并串转换啊？我这有程序看不懂，高手给详细解释下，谢谢

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity P16_SERIAL is
port(
clk:in std_logic;
din_valid :in std_logic;
din :in std_logic_vector(15 downto 0);
dout :out std_logic;
dout_valid : out std_logic;
reset: in std_logic);

end P16_SERIAL;

architecture Behavioral of P16_SERIAL is

signal shiftreg : std_logic_vector(15 downto 0);
signal count : std_logic_vector(4 downto 0);
signal hold : std_logic;
begin

process (clk,reset)
begin
if (reset='1') then
count<="00000";
hold<='0';
shiftreg <= (others=>'0');
elsif (clk 'event and clk='1') then
if(din_valid='1')then
hold <='1';
count<="00000";
shiftreg <= din;
else
if(hold='1') then
if (count ="01111") then
count<=(others=>'0');
hold <='0';
else
count<= count +1 ;
end if;

shiftreg(15 downto 1) <= shiftreg(14 downto 0);

end if;
end if;
end if;
end process;

process (clk,reset)
begin
if (reset='1') then
dout_valid<='0';
dout<='0';
elsif (clk 'event and clk='1') then
dout<=shiftreg(15);
if(hold='1') then
dout_valid<='1';
else
dout_valid<='0';
end if;
end if;

end process;

end Behavioral;

Answer 1

主要就是“shiftreg(15 downto 1) <= shiftreg(14 downto 0)”这句话的，其他是控制信号的。用count 来控制16位数据一次输出的。并串转换，你的程序是16位化为16个串行的时钟输出out<=shiftreg(15);。

Answer 2

第一个process是 串行
第二个process 是 并行

Answer 3

上边串，下边并