Question

VHDL求解，一段计数程序。小弟不是伸手党，但实在没辙了。先谢过大神了。

architecture art of count is
signal secg,secs: std_logic_vector(3 downto 0);--secg,是个位，secs是十位。
signal co: std_logic;
begin
process(cl_r,clk,add) is
begin
if cl_r='0' then
secg<="0000";secs<="0000";co<='0';
elsif clk='1'and clk'event then
if secg="1001" and secs="0101" then
secg<="0000";secs<="0000";co<='1';
elsif secg="1001" then
secs<=secs+1;secg<="0000";co<='0';
elsif secg<"1001" then
secg<=secg+1;
end if;
end if;
if add'event and add='1' then--想要add按一次，secg就加1.
secg<= secg+1;
end if;
c<=co;
ssec<=secs;
gsec<=secg;
end process;
end architecture;

错误：
Error (10820): Netlist error at count.vhd(28): can't infer register for secg[0] because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at count.vhd(28): can't infer register for secg[1] because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at count.vhd(28): can't infer register for secg[2] because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at count.vhd(28): can't infer register for secg[3] because its behavior depends on the edges of multiple distinct clocks
Error (10822): HDL error at count.vhd(19): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at count.vhd(28): couldn't implement registers for assignments on this clock edge

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count IS
PORT(clk : IN STD_LOGIC;
cl_r : IN STD_LOGIC;
add : IN STD_LOGIC;
c : OUT STD_LOGIC;
ssec : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gsec : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END count;
architecture art of count is
signal secg,secs: std_logic_vector(3 downto 0);--secg,是个位，secs是十位。
signal co: std_logic;
begin
process(clk,cl_r,add) is
begin
if cl_r='0' then
secg<="0000";
secs<="0000";
co<='0';
elsif clk='1'and clk'event then
if(add='1')then
secg<= secg+1;
else
if secg="1001" and secs="0101" then
secg<="0000";
secs<="0000";
co<='1';
elsif secg="1001" then
secs<=secs+1;
secg<="0000";
co<='0';
elsif secg<"1001" then
secg<=secg+1;
end if;
end if;
end if;
c<=co;
ssec<=secs;
gsec<=secg;
end process;
end architecture;

不能同时为secg设置两个触发条件

追问

劳大哥费心了，但是你放在IF语句里面，但是不管有没有ADD，只要来一个上升沿都会加1啊，这样没额外加。

追答

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count IS
PORT(clk : IN STD_LOGIC;
cl_r : IN STD_LOGIC;
add : IN STD_LOGIC;
c : OUT STD_LOGIC;
ssec : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gsec : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END count;
architecture art of count is
signal secg,secs: std_logic_vector(3 downto 0);
signal co: std_logic;
begin
process(clk,cl_r,add) is
begin
if cl_r='0' then
secg<="0000";
secs<="0000";
co<='0';
elsif clk='1'and clk'event then
if(add='1')then
secg<= secg+1;
end if;
if secg="1001" and secs="0101" then
secg<="0000";
secs<="0000";
co<='1';
elsif secg="1001" then
secs<=secs+1;
secg<="0000";
co<='0';
elsif secg<"1001" then
secg<=secg+1;
end if;
end if;
c<=co;
ssec<=secs;
gsec<=secg;
end process;
end architecture;

那天都上床睡觉了 睡着前突然想到写错了..后来没法改了就补了条评论
这次应该差不多 可以试试

追问

大哥，我也觉得你的逻辑对着呢。

  可是，为什么放出来还是不行呢。。。。。我要哭了。。

追答

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count IS
PORT(clk : IN STD_LOGIC;
cl_r : IN STD_LOGIC;
add : IN STD_LOGIC;
c : OUT STD_LOGIC;
ssec : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gsec : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END count;
architecture art of count is
--signal secg,secs: std_logic_vector(3 downto 0);--secg,�Ǹ�λ��secs��ʮλ��
signal co: std_logic;
begin
process(clk,cl_r,add) is
variable secg,secs: std_logic_vector(3 downto 0);
begin
if cl_r='0' then
secg:="0000";
secs:="0000";
co<='0';
elsif clk='1'and clk'event then
if(add='1')then
secg:= secg+1;
end if;
if secg="1001" and secs="0101" then
secg:="0000";
secs:="0000";
co<='1';
elsif secg="1001" then
secs:=secs+1;
secg:="0000";
co<='0';
elsif secg<"1001" then
secg:=secg+1;
end if;
end if;
c<=co;
ssec<=secs;
gsec<=secg;
end process;
end architecture;

额 好久不写忘了signal和variable的区别了... 这个仿真差不多
只功能仿真是够用了

追问

大哥，这两天谢谢你了，，确实牛人啊， 语句对了，

  我刚一看时序图就知道自己一开始的程序框架都没对，因为要的是不管什么时候ADD只要有按键，都会加1，结果放在IF语句里了，就只有CLK有上升沿的时候才有效，看来还得重新理思路，

  真的很感谢。，

（圆里都是对的，方框都不对。

）

Answer 2

你这太乱了，要养成好的习惯，大小写，空格什么的。
个人觉得主要原因是在一个Process中，不能有两个判别上升沿的语句，在你的程序中判断了clk和add两个信号值的上升沿，所以会错误。
可以把判断add的上升沿去掉，然后定义两个中间信号
Sginal:add1,add2:STD_LOGIC;
add1<=add;
add2<=add1;
IF(add1 AND NOT add2 = '1')THEN
这样的方式来避免在同一个Process中有两个判断上升沿的现象。

不知对错，仅供参考。