Question

FPGA仿真 modelsim error ?

# ** Error: E:/program/FPGA/The First Led/Led.v(18): A begin/end block was found with an empty body. This is permitted in SystemVerilog, but not permitted in Verilog. Please look for any stray semicolons.
# ** Error: C:/altera/11.0/modelsim_ae/win32aloem/vlog failed.

`timescale 1 ns/ 1 ps
module Led_vlg_tst();
// constants
// general purpose registers
reg clk;
reg rst_n;
// wires
wire led_d1;
// assign statements (if any)
Led i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led_d1(led_d1),
.rst_n(rst_n)
);
initial begin
clk = 0;
forever
#10 clk = ~clk;
end

initial begin
rst_n = 0;
#100;
rst_n = 1;
#5000;
$stop;
end

endmodule
////////////////////////////////////////////////////////////////////////////
module Led(
clk,rst_n,led_d1
);
input clk;
input rst_n;
output led_d1;
reg led;
reg[15:0] cnt;
parameter COUNT = 49;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= 16'd0;
else if(cnt == COUNT)
begin
led <= !led;;
cnt <= 16'b0;
end
else cnt <= cnt + 16'd1;
end
assign led_d1 = led;

endmodule

Answer 1

“led <= !led;;”多了个分号