Question

急急急！！！用vhdl语言写一个计数器程序 下面的错误不知道哪里错了求指教

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timer is
port( data_in:in std_logic_vector(7 downto 0);
rest,clock,start: in std_logic;
ring:out std_logic
) ;
end timer;
architecture behav of timer is
begin
process(reset,clock)
variable counter:std_logic_vector(7 downto 0); --变量的声明
variable state:integer range 0 to 3; --变量的声明
begin
if reset='0'then
ring <='0';
state:=0;
elsif clock'event and clock='1'then
case state is
when 0 =>
ring <= '0';
counter:="00000000";
if start='1' then
state:=1;
else
state:=0;
end if;
when 1 =>
counter<= data_in;
if start= '1' then
state:=1;
else
state:=0;
when 2 =>
start<= '0';
if counter=1 then
counter :="00001000";
else
counter=counter-1;
end if;
when 3 =>
ring <= '0';
if counter/=1 then
counter=counter-1;
else state:=0;
end if;
end case;
end process;
end behav;
Error (10500): VHDL syntax error at timer.vhd(35) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at timer.vhd(40) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at timer.vhd(42) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at timer.vhd(45) near text "="; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at timer.vhd(48) near text "case"; expecting "if"

Answer 1

when 1子句中的if语句最后缺少end if;