Question

VHDL一个小程序的错误

报错信息：
ERROR:HDLCompiler:76 - "H:\EDA\ISE project\traffic\counter_display.vhd" Line 34: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition
下面是报错部分的程序，我想实现的是一个倒数计数器的功能：
if(clk'event and clk='1' and state="00" and et='0')then count:=0;stop:=0;
elsif(clk'event and clk='1' and state="01" and et='0')then count:=2;stop:=0;
elsif(clk'event and clk='1' and state="10" and et='0')then count:=5;stop:=0;
elsif(clk'event and clk='1' and state="11" and et='0')then stop:=1;
elsif(clk'event and clk='1' and et='1')then
if(count=0)then count:=9;
else count:=count-1;
end if;
else null;
end if;

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Answer 1

不要将信号的边沿检测搞成这么多。写成下面这样试试看：
if clk'event and clk='1' then
if et='0' then
case state is
when "00" => count := 0; stop := 0;
when "01" => count := 2; stop := 0;
when "10" => count := 5; stop := 0;
when others => stop := 1;
end case;
else if count=0 then count := 9;
else count := count-1;
end if;
end if;
end if;