Question

在用quartusII验证vhdl程序时发现的错误，是书上的例子.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
port( in1: in std_logic;
in2: in std_logic;
cntl: bit;
pout: out bit_vector);
end adder;
architecture func of adder is
begin
process(cntl)
begin
if(cntl='1') then pout<=in1+in2;
end if;
end process;
end func;
提示错误：Error (10327): VHDL error at adder.vhd(16): can't determine definition of operator ""+"" -- found 0 possible definitions

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
port( in1: in std_logic;
in2: in std_logic;
cntl: std_logic;
pout: out std_logic);
end adder;
architecture func of adder is
begin
process(cntl)
begin
if(cntl='1') then pout<=in1 and in2;
end if;
end process;
end func;
帮你改了下 应该可以用了

Answer 2

in1+in2 逻辑量不能加 要写成and or 之类的