‏module test-ple(
‏ input reg [7:0] a;
‏ input [7:0] b;
‏ ouput reg yout;
‏ )
‏ wire [3:0] temp1, temph;
‏ always @ (a) begin
‏ assign templ = a[3:0] & b[7:4];
‏ assign temph = a[7:4] & b[3:0];
‏ yout = {temph, templ};
‏ end
‏endmodule
‎